1. Field of the Invention
The present invention relates generally to protection devices for integrated circuits, and more particularly to a method and apparatus for protecting integrated circuits from various electrical transients, including electrostatic discharge (ESD).
2. Description of the Related Art
As technology in very large scale integration (VLSI) improves thereby further decreasing circuit geometries, integrated circuits (ICs) become more susceptible to damage from electrical over stress (EOS) events. EOS events include very fast transients, such as electrostatic discharge (ESD).
ESD is a well-known cause of operation failure of integrated circuits. The buildup of electrostatic charge on personnel and equipment during the manufacture and use of integrated circuits can reach potentials as high as 30,000 volts with respect to an ESD reference point. During an ESD event, this charge is transferred between one or more pins of the device, i.e., integrated circuit, and another conducting object in a time period that is typically less than one microsecond. The electrostatic discharge may occur during manufacturing or testing when the integrated circuit is non-operating, or it may occur when the integrated circuit is installed in a device and is operating. Integrated circuits are particularly susceptible to ESD damage during handling in a manufacturing, testing or printed circuit board assembly environment. An electrostatic discharge through an integrated circuit can permanently damage the integrated circuit through several failure mechanisms, including the dielectric breakdown of oxides and other thin layers, and the melting of semiconductive material such as silicon, resulting in excessive leakage currents and open or short circuits within the integrated circuit.
Accordingly, manufacturers take considerable care to protect semiconductor devices from such ESD events. Protection circuits may typically be connected to all Input/Output (I/O) pads of an integrated circuit to safely dissipate the energy associated with ESD events without causing any damage to the circuitry internal to the device. Protection circuits have also been connected to the power supply pads, or between power supply buses to prevent such damage to internal circuits.
FIG. 1 illustrates one conventional device 10 for protecting a semiconductor circuit from ESD events. Device 10 is adapted for use in connection with a plurality of input pads, such as input pads 12a, 12b, . . . 12n. Each of the input pads 12a-12n are further connected to an input buffer (not shown) as is known in the art. Device 10 includes a plurality of diode clamping circuits, such as circuits 14a, 14b, 14n. The positive power supply bus for the integrated circuit, designated VCC, is protected against ESD with respect to the negative power supply bus of the integrated circuit, VSS, and vice versa, using a core clamp 16. Conventional core clamps, including field snap-back (FSB) transistors, metal-oxide-semiconductor (MOS) devices, diode strings, Silicon Controlled Rectifiers (SCR), Low Voltage Trigger Silicon Controlled Rectifiers (LTVSCR) and the like, are well known in the art.
There are problems, however, with conventional core clamps, as they have been found to be ineffective in certain circumstances. For example, with a conventional core clamp, the protective devices may be insufficient to completely protect silicide layers within the integrated circuit from the heat generated by the power dissipation of the protective device during an ESD event. Furthermore, the voltage drop during an ESD event across the series combination of the forward biased diode (in diode clamping circuit 14) and the core clamp 16 is typically too high to protect a pull-down device (not shown) connected to a pad 12. Additionally, the voltage levels could also be too high to-protect the input buffers connected to the pads.
The present invention alleviates the problems associated with the prior art and provides an adjustable setpoint ESD core clamp.
In accordance with the present invention, a core clamp includes an SCR whose P+N trigger junction is referenced to a diode stack. The SCR is non-avalanche triggered into a low impedance state at a set value of VCC, as determined by the diode stack, which allows the ESD device to turn on at a lower voltage, thereby protecting internal circuitry.
These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.